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sn74ahct1g32 scls320o ? march 1996 ? revised december 2014 sn74ahct1g32 single 2-input positive-or gate 1 features 2 applications 1 ? operating range of 4.5 v to 5.5 v ? i/o modules; analog plc/dcs inputs ? max t pd of 8 ns at 5 v ? server motherboards ? low power consumption, 10- a max i cc ? automotive clusters ? 8-ma output drive at 5 v ? motor drives and controls ? inputs are ttl-voltage compatible ? dlp front projection systems ? latch-up performance exceeds 250 ma ? tvs per jesd 17 ? set-top-boxes ? esd protection exceeds jesd 22 ? audio ? 2000-v human-body model 3 description ? 200-v machine model the sn74ahct1g32 device is a single 2-input ? 1000-v charged-device model positive-or gate. the device performs the boolean function in positive logic. device information (1) part number package body size (nom) sot-23 (5) 2.90 mm x 1.60 mm sn74ahct1g32 sc-70 (5) 2.00 mm x 1.30 mm sot-553 (5) 1.65 mm x 1.20 mm (1) for all available packages, see the orderable addendum at the end of the data sheet. 4 simplified schematic 1 an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. production data. y a b or y a ? b = + = ab y tools & software technical documents sample &buy productfolder support &community
sn74ahct1g32 scls320o ? march 1996 ? revised december 2014 www.ti.com table of contents 9.1 overview ................................................................... 7 1 features .................................................................. 1 9.2 functional block diagram ......................................... 7 2 applications ........................................................... 1 9.3 feature description ................................................... 7 3 description ............................................................. 1 9.4 device functional modes .......................................... 7 4 simplified schematic ............................................. 1 10 application and implementation .......................... 8 5 revision history ..................................................... 2 10.1 application information ............................................ 8 6 pin configuration and functions ......................... 3 10.2 typical application ................................................. 8 7 specifications ......................................................... 4 11 power supply recommendations ....................... 9 7.1 absolute maximum ratings ...................................... 4 12 layout ................................................................... 10 7.2 esd ratings ............................................................ 4 12.1 layout guidelines ................................................. 10 7.3 recommended operating conditions ....................... 4 12.2 layout example .................................................... 10 7.4 thermal information .................................................. 4 13 device and documentation support ................. 10 7.5 electrical characteristics ........................................... 5 13.1 trademarks ........................................................... 10 7.6 switching characteristics .......................................... 5 13.2 electrostatic discharge caution ............................ 10 7.7 operating characteristics .......................................... 5 13.3 glossary ................................................................ 10 7.8 typical characteristics .............................................. 5 14 mechanical, packaging, and orderable 8 parameter measurement information .................. 6 information ........................................................... 10 9 detailed description .............................................. 7 5 revision history changes from revision n (june 2005) to revision o page ? added applications , device information table, pin functions table, esd ratings table, thermal information table, typical characteristics , feature description section, device functional modes , application and implementation section, power supply recommendations section, layout section, device and documentation support section, and mechanical, packaging, and orderable information section. ................................................................................................. 1 ? deleted ordering information table. ....................................................................................................................................... 1 ? changed max operating temperature to 125 c in recommended operating conditions table. ......................................... 4 2 submit documentation feedback copyright ? 1996 ? 2014, texas instruments incorporated product folder links: sn74ahct1g32
sn74ahct1g32 www.ti.com scls320o ? march 1996 ? revised december 2014 6 pin configuration and functions pin functions pin type description no. name 1 a i input a 2 b i input b 3 gnd ? ground pin 4 y o output y 5 v cc ? power pin copyright ? 1996 ? 2014, texas instruments incorporated submit documentation feedback 3 product folder links: sn74ahct1g32 3 2 4 5 1 a v cc y b gnd dbv package (top view) dck package (top view) 3 2 4 5 1 a v cc y b gnd 3 2 4 5 1 a v cc y b gnd drl package (top view) see mechanical drawings for dimensions.
sn74ahct1g32 scls320o ? march 1996 ? revised december 2014 www.ti.com 7 specifications 7.1 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) (1) min max unit v cc supply voltage range ? 0.5 7 v v i input voltage range (2) ? 0.5 7 v v o output voltage range (2) ? 0.5 v cc + 0.5 v i ik input clamp current v i < 0 ? 20 ma i ok output clamp current v o < 0 or v o > v cc 20 ma i o continuous output current v o = 0 to v cc 25 ma continuous current through v cc or gnd 50 ma t stg storage temperature range ? 65 150 c (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) the input and output voltage ratings may be exceeded if the input and output current ratings are observed. 7.2 esd ratings value unit human body model (hbm), per ansi/esda/jedec js-001, all pins (1) 2000 v (esd) electrostatic discharge v charged device model (cdm), per jedec specification jesd22-c101, 1000 all pins (2) (1) jedec document jep155 states that 500-v hbm allows safe manufacturing with a standard esd control process. (2) jedec document jep157 states that 250-v cdm allows safe manufacturing with a standard esd control process. 7.3 recommended operating conditions over operating free-air temperature range (unless otherwise noted) (1) min max unit v cc supply voltage 4.5 5.5 v v ih high-level input voltage 2 v v il low-level input voltage 0.8 v v i input voltage 0 5.5 v v o output voltage 0 v cc v i oh high-level output current ? 8 ma i ol low-level output current 8 ma ? t/ ? v input transition rise or fall rate 20 ns/v t a operating free-air temperature ? 40 125 c (1) all unused inputs of the device must be held at v cc or gnd to ensure proper device operation. refer to the ti application report, implications of slow or floating cmos inputs ( scba004 ). 7.4 thermal information sn74ahct1g32 thermal metric (1) dbv dck drl unit 5 pins r ja junction-to-ambient thermal resistance 231.3 287.6 328.7 r jc(top) junction-to-case (top) thermal resistance 119.9 97.7 105.1 r jb junction-to-board thermal resistance 60.6 65. 150.3 c/w jt junction-to-top characterization parameter 17.8 2.0 6.9 jb junction-to-board characterization parameter 60.1 64.2 148.4 (1) for more information about traditional and new thermal metrics, see the ic package thermal metrics application report ( spra953 ). 4 submit documentation feedback copyright ? 1996 ? 2014, texas instruments incorporated product folder links: sn74ahct1g32
sn74ahct1g32 www.ti.com scls320o ? march 1996 ? revised december 2014 7.5 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) t a = 25 c ? 40 c to 85 c ? 40 c to 125 c paramet test conditions v cc unit er min typ max min max min max i oh = ? 50 a 4.4 4.5 4.4 4.4 v oh 4.5 v v i oh = ? 8 ma 3.94 3.8 3.8 i ol = 50 a 0.1 0.1 0.1 v ol 4.5 v v i ol = 8 ma 0.36 0.44 0.44 0 v to i i v i = 5.5 v or gnd 0.1 1 1 a 5.5 v i cc v i = v cc or gnd, i o = 0 5.5 v 1 10 10 a one input at 3.4 v, ? i cc (1) 5.5 v 1.35 1.5 1.5 ma other inputs at v cc or gnd c i v i = v cc or gnd 5 v 2 10 10 10 pf (1) this is the increase in supply current for each input at one of the specified ttl voltage levels, rather than 0 v or v cc . 7.6 switching characteristics over recommended operating free-air temperature range, v cc = 5 v 0.5 v (unless otherwise noted) (see figure 2 ) t a = 25 c ? 40 c to 85 c ? 40 c to 125 c from to load parameter unit (input) (output) capacitance min typ max min max min max t plh 5 6.9 1 8 1 9 a or b y c l = 15 pf ns t phl 5 6.9 1 8 1 9 t plh 5.5 7.9 1 9 1 10 a or b y c l = 50 pf ns t phl 5.5 7.9 1 9 1 10 7.7 operating characteristics v cc = 5 v, t a = 25 c parameter test conditions typ unit c pd power dissipation capacitance no load, f = 1 mhz 11.5 pf 7.8 typical characteristics figure 1. tpd vs temperature copyright ? 1996 ? 2014, texas instruments incorporated submit documentation feedback 5 product folder links: sn74ahct1g32 temperature ( q c) tpd (ns) -100 -50 0 50 100 150 0 1 2 3 4 5 6 d001 tpd in ns
sn74ahct1g32 scls320o ? march 1996 ? revised december 2014 www.ti.com 8 parameter measurement information figure 2. load circuit and voltage waveforms 6 submit documentation feedback copyright ? 1996 ? 2014, texas instruments incorporated product folder links: sn74ahct1g32 50% v cc 3 v3 v 0 v0 v t h t su voltage waveforms setup and hold times data input t plh t phl t phl t plh v oh v oh v ol v ol 3 v0 v 50% v cc 50% v cc input out-of-phase output in-phase output timing input 50% v cc voltage waveforms propagation delay times inverting and noninverting outputs output control output waveform 1 s1 at v cc (see note b) output waveform 2 s1 at gnd (see note b) v ol v oh t pzl t pzh t plz t phz v cc 0 v 50% v cc v ol + 0.3 v 50% v cc 0 v 3 v voltage waveforms enable and disable times low- and high-level enabling t plh /t phl t plz /t pzl t phz /t pzh open drain open v cc gnd v cc test s1 3 v0 v t w voltage waveforms pulse duration input notes: a. c l includes probe and jig capacitance. b. waveform 1 is for an output with internal conditions such that the output i s low, except when disabled by the output control. waveform 2 is for an output with internal conditions such that the output is hi gh, except when disabled by the output control. c. all input pulses are supplied by generators having the fol lowing characteristics: prr 1 mhz, z o = 50 , t r 3 ns, t f 3 ns . d. the outputs are measured one at a time, with one input trans ition per measurement. e. all parameters and waveforms are not applicable to all dev ices. from output under test c l (see note a) load circuit for 3-state and open-drain outputs s1 v cc r l = 1 k gnd from output under test c l (see note a) test point load circuit for totem-pole outputs open v oh ? 0.3 v 1.5 v 1.5 v 1.5 v 1.5 v 1.5 v 1.5 v 1.5 v 1.5 v 1.5 v
sn74ahct1g32 www.ti.com scls320o ? march 1996 ? revised december 2014 9 detailed description 9.1 overview the sn74ahct1g32 device is a single 2-input positive-or gate. the device performs the boolean function in positive logic. the device has ttl inputs that allow up translation from 3.3 v to 5 v. the inputs are high impedance when v cc = 0 v. 9.2 functional block diagram figure 3. logic diagram (positive logic) 9.3 feature description ? slow rise and fall time on outputs allow for low noise outputs. ? ttl inputs ? allows up translation from 3.3 v to 5 v 9.4 device functional modes table 1. function table inputs output y a b h x h x h h l l l copyright ? 1996 ? 2014, texas instruments incorporated submit documentation feedback 7 product folder links: sn74ahct1g32 y a b or y a ? b = + = ab y
sn74ahct1g32 scls320o ? march 1996 ? revised december 2014 www.ti.com 10 application and implementation note information in the following applications sections is not part of the ti component specification, and ti does not warrant its accuracy or completeness. ti ? s customers are responsible for determining suitability of components for their purposes. customers should validate and test their design implementation to confirm system functionality. 10.1 application information sn74ahct1g125 is a low-drive cmos device that can be used for a multitude of bus interface type applications where output ringing is a concern. the low drive and slow edge rates will minimize overshoot and undershoot on the outputs. the ttl inputs can accept voltages down to 3.3 v and translate up to 5 v. 10.2 typical application figure 4. typical application schematic 10.2.1 design requirements this device uses cmos technology and has balanced output drive. care should be taken to avoid bus contention because it can drive currents that would exceed maximum limits. the high drive will also create fast edges into light loads, so routing and load conditions should be considered to prevent ringing. 10.2.2 detailed design procedure 1. recommended input conditions ? for rise time and fall time specifications, see t/ v in the recommended operating conditions table. ? for specified high and low levels, see v ih and v il in the recommended operating conditions table. 2. recommend output conditions ? load currents should not exceed 25 ma per output and 50 ma total for the part. ? outputs should not be pulled above v cc . 8 submit documentation feedback copyright ? 1996 ? 2014, texas instruments incorporated product folder links: sn74ahct1g32 v cc 0.1 f 3.3 v or 5 v 5-v accessory c or system logic 5-v regulated
sn74ahct1g32 www.ti.com scls320o ? march 1996 ? revised december 2014 typical application (continued) 10.2.3 application curves figure 5. switching characterstics comparison 11 power supply recommendations the power supply can be any voltage between the min and max supply voltage rating located in the recommended operating conditions table. each v cc pin should have a good bypass capacitor to prevent power disturbance. for devices with a single supply, 0.1 f is recommended. if there are multiple v cc pins, 0.01 f or 0.022 f is recommended for each power pin. it is acceptable to parallel multiple bypass caps to reject different frequencies of noise. a 0.1 f and 1 f are commonly used in parallel. the bypass capacitor should be installed as close to the power pin as possible for best results. copyright ? 1996 ? 2014, texas instruments incorporated submit documentation feedback 9 product folder links: sn74ahct1g32
sn74ahct1g32 scls320o ? march 1996 ? revised december 2014 www.ti.com 12 layout 12.1 layout guidelines when using multiple bit logic devices, inputs should not float. in many cases, functions or parts of functions of digital logic devices are unused. some examples are when only two inputs of a triple-input and gate are used, or when only 3 of the 4-buffer gates are used. such input pins should not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. specified in figure 6 are rules that must be observed under all circumstances. all unused inputs of digital logic devices must be connected to a high or low bias to prevent them from floating. the logic level that should be applied to any particular unused input depends on the function of the device. generally they will be tied to gnd or v cc , whichever makes more sense or is more convenient. it is acceptable to float outputs unless the part is a transceiver. if the transceiver has an output enable pin, it will disable the outputs section of the part when asserted. this will not disable the input section of the i/os so they also cannot float when disabled. 12.2 layout example figure 6. layout diagram 13 device and documentation support 13.1 trademarks all trademarks are the property of their respective owners. 13.2 electrostatic discharge caution these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. 13.3 glossary slyz022 ? ti glossary . this glossary lists and explains terms, acronyms, and definitions. 14 mechanical, packaging, and orderable information the following pages include mechanical, packaging, and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and revision of this document. for browser-based versions of this data sheet, refer to the left-hand navigation. 10 submit documentation feedback copyright ? 1996 ? 2014, texas instruments incorporated product folder links: sn74ahct1g32 v cc unused input input output input unused input output
package option addendum www.ti.com 26-sep-2018 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples 74ahct1g32dbvrg4 active sot-23 dbv 5 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 b32g 74AHCT1G32DCKRE4 active sc70 dck 5 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 bg3 74ahct1g32dckrg4 active sc70 dck 5 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 bg3 sn74ahct1g32dbvr active sot-23 dbv 5 3000 green (rohs & no sb/br) cu nipdau | cu sn level-1-260c-unlim -40 to 125 (b323, b32g, b32j, b32l, b32s) sn74ahct1g32dbvt active sot-23 dbv 5 250 green (rohs & no sb/br) cu nipdau | cu sn level-1-260c-unlim -40 to 125 (b323, b32g, b32l, b32s) sn74ahct1g32dck3 active sc70 dck 5 3000 pb-free (rohs) cu snbi level-1-260c-unlim -40 to 85 bgy sn74ahct1g32dckr active sc70 dck 5 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 (bg3, bgg, bgj, bg l, bgs) sn74ahct1g32dckt active sc70 dck 5 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 (bg3, bgg, bgl, bg s) sn74ahct1g32drlr active sot-5x3 drl 5 4000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 bgs (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) rohs: ti defines "rohs" to mean semiconductor products that are compliant with the current eu rohs requirements for all 10 rohs substances, including the requirement that rohs substance do not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, "rohs" products are suitable for use in specified lead-free processes. ti may reference these types of products as "pb-free". rohs exempt: ti defines "rohs exempt" to mean products that contain lead but are compliant with eu rohs pursuant to a specific eu rohs exemption. green: ti defines "green" to mean the content of chlorine (cl) and bromine (br) based flame retardants meet js709b low halogen requirements of <=1000ppm threshold. antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature.
package option addendum www.ti.com 26-sep-2018 addendum-page 2 (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. other qualified versions of sn74ahct1g32 : ? automotive: sn74ahct1g32-q1 note: qualified version definitions: ? automotive - q100 devices qualified for high-reliability automotive applications targeting zero defects
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant 74ahct1g32dbvrg4 sot-23 dbv 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 q3 74ahct1g32dckrg4 sc70 dck 5 3000 178.0 9.2 2.4 2.4 1.22 4.0 8.0 q3 sn74ahct1g32dbvr sot-23 dbv 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 q3 sn74ahct1g32dbvr sot-23 dbv 5 3000 180.0 8.4 3.23 3.17 1.37 4.0 8.0 q3 sn74ahct1g32dbvr sot-23 dbv 5 3000 178.0 9.2 3.3 3.23 1.55 4.0 8.0 q3 sn74ahct1g32dbvt sot-23 dbv 5 250 178.0 9.2 3.3 3.23 1.55 4.0 8.0 q3 sn74ahct1g32dbvt sot-23 dbv 5 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 q3 sn74ahct1g32dckr sc70 dck 5 3000 180.0 9.2 2.3 2.55 1.2 4.0 8.0 q3 sn74ahct1g32dckr sc70 dck 5 3000 180.0 8.4 2.47 2.3 1.25 4.0 8.0 q3 sn74ahct1g32dckr sc70 dck 5 3000 178.0 9.0 2.4 2.5 1.2 4.0 8.0 q3 sn74ahct1g32dckr sc70 dck 5 3000 178.0 9.2 2.4 2.4 1.22 4.0 8.0 q3 sn74ahct1g32dckt sc70 dck 5 250 178.0 9.2 2.4 2.4 1.22 4.0 8.0 q3 sn74ahct1g32dckt sc70 dck 5 250 180.0 9.2 2.3 2.55 1.2 4.0 8.0 q3 sn74ahct1g32dckt sc70 dck 5 250 178.0 9.0 2.4 2.5 1.2 4.0 8.0 q3 sn74ahct1g32drlr sot-5x3 drl 5 4000 180.0 8.4 1.98 1.78 0.69 4.0 8.0 q3 package materials information www.ti.com 15-sep-2018 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) 74ahct1g32dbvrg4 sot-23 dbv 5 3000 180.0 180.0 18.0 74ahct1g32dckrg4 sc70 dck 5 3000 180.0 180.0 18.0 sn74ahct1g32dbvr sot-23 dbv 5 3000 180.0 180.0 18.0 sn74ahct1g32dbvr sot-23 dbv 5 3000 202.0 201.0 28.0 sn74ahct1g32dbvr sot-23 dbv 5 3000 180.0 180.0 18.0 sn74ahct1g32dbvt sot-23 dbv 5 250 180.0 180.0 18.0 sn74ahct1g32dbvt sot-23 dbv 5 250 180.0 180.0 18.0 sn74ahct1g32dckr sc70 dck 5 3000 205.0 200.0 33.0 sn74ahct1g32dckr sc70 dck 5 3000 202.0 201.0 28.0 sn74ahct1g32dckr sc70 dck 5 3000 180.0 180.0 18.0 sn74ahct1g32dckr sc70 dck 5 3000 180.0 180.0 18.0 sn74ahct1g32dckt sc70 dck 5 250 180.0 180.0 18.0 sn74ahct1g32dckt sc70 dck 5 250 205.0 200.0 33.0 sn74ahct1g32dckt sc70 dck 5 250 180.0 180.0 18.0 sn74ahct1g32drlr sot-5x3 drl 5 4000 202.0 201.0 28.0 package materials information www.ti.com 15-sep-2018 pack materials-page 2

www.ti.com package outline c typ 0.22 0.08 0.25 3.0 2.6 2x 0.95 1.9 1.45 max typ 0.15 0.00 5x 0.5 0.3 typ 0.6 0.3 typ 8 0 1.9 a 3.05 2.75 b 1.75 1.45 (1.1) sot-23 - 1.45 mm max height dbv0005a small outline transistor 4214839/c 04/2017 notes: 1. all linear dimensions are in millimeters. any dimensions in parenthesis are for reference only. dimensioning and tolerancing per asme y14.5m. 2. this drawing is subject to change without notice. 3. refernce jedec mo-178. 0.2 c a b 1 3 4 5 2 index area pin 1 gage plane seating plane 0.1 c scale 4.000
www.ti.com example board layout 0.07 max arround 0.07 min arround 5x (1.1) 5x (0.6) (2.6) (1.9) 2x (0.95) (r0.05) typ 4214839/c 04/2017 sot-23 - 1.45 mm max height dbv0005a small outline transistor notes: (continued) 4. publication ipc-7351 may have alternate designs. 5. solder mask tolerances between and around signal pads can vary based on board fabrication site. symm land pattern example exposed metal shown scale:15x pkg 1 3 4 5 2 solder mask opening metal under solder mask solder mask defined exposed metal metal solder mask opening non solder mask defined (preferred) solder mask details exposed metal
www.ti.com example stencil design (2.6) (1.9) 2x(0.95) 5x (1.1) 5x (0.6) (r0.05) typ sot-23 - 1.45 mm max height dbv0005a small outline transistor 4214839/c 04/2017 notes: (continued) 6. laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. ipc-7525 may have alternate design recommendations. 7. board assembly site may have different recommendations for stencil design. solder paste example based on 0.125 mm thick stencil scale:15x symm pkg 1 3 4 5 2
www.ti.com package outline c typ 0.22 0.08 0.25 3.0 2.6 2x 0.95 1.9 1.45 max typ 0.15 0.00 5x 0.5 0.3 typ 0.6 0.3 typ 8 0 1.9 a 3.05 2.75 b 1.75 1.45 (1.1) sot-23 - 1.45 mm max height dbv0005a small outline transistor 4214839/c 04/2017 notes: 1. all linear dimensions are in millimeters. any dimensions in parenthesis are for reference only. dimensioning and tolerancing per asme y14.5m. 2. this drawing is subject to change without notice. 3. refernce jedec mo-178. 0.2 c a b 1 3 4 5 2 index area pin 1 gage plane seating plane 0.1 c scale 4.000
www.ti.com example board layout 0.07 max arround 0.07 min arround 5x (1.1) 5x (0.6) (2.6) (1.9) 2x (0.95) (r0.05) typ 4214839/c 04/2017 sot-23 - 1.45 mm max height dbv0005a small outline transistor notes: (continued) 4. publication ipc-7351 may have alternate designs. 5. solder mask tolerances between and around signal pads can vary based on board fabrication site. symm land pattern example exposed metal shown scale:15x pkg 1 3 4 5 2 solder mask opening metal under solder mask solder mask defined exposed metal metal solder mask opening non solder mask defined (preferred) solder mask details exposed metal
www.ti.com example stencil design (2.6) (1.9) 2x(0.95) 5x (1.1) 5x (0.6) (r0.05) typ sot-23 - 1.45 mm max height dbv0005a small outline transistor 4214839/c 04/2017 notes: (continued) 6. laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. ipc-7525 may have alternate design recommendations. 7. board assembly site may have different recommendations for stencil design. solder paste example based on 0.125 mm thick stencil scale:15x symm pkg 1 3 4 5 2

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